Huawei's newest smartphone features China's most advanced…

TechInsights, a respected microelectronics research company, has examined Huawei's latest HiSilicon Kirin 9030 processor and discovered that it was made using what they call N+3 fabrication technology, the most advanced manufacturing process that China's Semiconductor Manufacturing International Corp. (SMIC) has to offer. Although TechInsights claims that SMIC's N+3 is a step towards 5nm, it lags behind 5nm-class fabrication technologies from leading chipmakers.

Huawei's HiSilicon Kirin 9030 and Kirin 9030 Pro are the company's latest system-on-chips (SoCs) that power Mate 80-series smartphones. The vanilla version reportedly has 12 cores, whereas the Pro version boasts with 14 cores, so both SoCs beat Huawei's eight-core Kirin 9000 from 2020 (made by TSMC using its 5nm-class process technology) in terms of core count, thus suggesting that the company has found a way to squeeze in more cores without significantly increasing power consumption, something that clearly implies on a new fabrication process.

Indeed, TechInsights's structural and dimensional analysis confirms that the Kirin 9030 is made using SMIC's N+3 manufacturing technology. Yet, as estimated by SemiAnalysis, SMIC's N+3 is not a 5nm-class fabrication process, as one might think, but rather something that sits between 7nm and 5nm and therefore is not a real generational leap. This still means that SMIC has managed to advance its most advanced manufacturing technology beyond N+1 (1^st Generation 7nm-class) and then N+2 (2^nd Generation 7nm-class) using equipment purchased before 2022, as well as some domestic tools.

"The Kirin 9030 is manufactured using SMIC’s N+3 process, a scaled extension of its previous 7nm (N+2) node," wrote Rajesh Krishnamurthy, an analyst with TechInsights. "However, in absolute terms, N+3 remains substantially less scaled than industry 5nm processes from TSMC and Samsung. While SMIC has executed notable innovations in DUV-based patterning and DTCO techniques, the process is expected to face significant yield challenges, particularly due to aggressively scaled metal pitch using DUV multi-patterning."

TechInsights's conclusion does not reveal much, but at least the wording makes it clear that N+3 is not a true generational leap, but an incremental stretch of SMIC's existing 7nm-class technology. By calling it a 'scaled extension' of N+2, the analysts are signaling that front-end scaling is largely exhausted: fin pitch (FP), contacted poly pitch (CPP), and fundamental transistor geometry have not moved meaningfully. Instead, SMIC is extracting remaining gains through DUV-driven DTCO and back-end-of-line (BEOL) tricks (something the company has already used to make its N+1 a viable alternative for 7nm-class nodes), rather than through a clean node transition comparable to TSMC or Samsung's 5nm-class processes.

The most important technical warning is the focus on aggressively scaled metal pitch using DUV multi-patterning, as multi-patterning is where the risk concentrates. Scaling BEOL with DUV requires several patterning steps that must line up extremely precisely, and each step adds to line roughness (via misalignment) and defect risk. Unlike FEOL, where performance degrades gradually, BEOL yield can collapse abruptly once overlay and variability budgets are exceeded, which must be a reason why TechInsights explicitly flags yield challenges rather than raw scaling limits.

In general, N+3 demonstrates that SMIC can still push density upwards without EUV, but only at rapidly rising cost and falling yield headroom. Such design decisions place the process firmly closer to a 7nm/6nm-class nodes rather than to 5nm-class nodes. Furthermore, it signals that SMIC's future progress will rely less on further lithographic shrink and more on design discipline via DTCO (which is not limitless, so to speak), innovative high-density libraries, and conservative clocks, because it looks like the foundry can only do this much on the FEOL level. Of course, advanced packaging remains the most viable path for SMIC's scaling going forward, but that does not really work for mobile and other low-power devices.

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